That’s important because adding a second step-say, by building them on separate wafers and then bonding the wafers together-could lead to misalignments that would destroy any potential circuits.Īt its heart, the process is a modification of the steps involved in making nanosheet transistors. Intel’s recipe for building stacked nanosheets is called a self-aligned process because it builds both devices in essentially the same step. But by stacking the transistors and adjusting the interconnects, the inverter’s area was cut in half. Even when the transistors sit side-by-side, as they do today, the arrangement is very compact. It requires two transistors, two connections to power, one input interconnect, and one output. Intel engineers used these devices to build the simplest CMOS logic circuit, an inverter. Shrinking circuits further will require stacking NMOS and PMOS devices. Instead of the main part of the transistor consisting of a vertical fin of silicon as it does today, the nanosheet’s channel region consists of multiple, horizontal, nanometers-thin sheets stacked atop one another.ĬMOS devices have evolved from planar to FinFET. The scheme starts by using what’s widely agreed to be the next generation transistor structure, called variously nanosheet, nanoribbon, nanowire, or gate-all-around device depending on who’s involved. The scheme effectively cut the footprint of a simple CMOS circuit in half, meaning a potential doubling of transistor density on future ICs. This week, at the IEEE International Electron Devices Meeting (IEDM), Intel showed a different way: stacking the pairs so that one is atop the other. These pairs have sat beside each other for decades, but if circuits are to continue shrinking they’re going to have to get closer still. Putting them together means that electricity should flow only when a bit changes, greatly cutting down on power consumption.
The same voltage signal that turns one of them on turns the other off. The logic circuits behind just about every digital device today rely on a pairing of two types of transistors-NMOS and PMOS.
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